[sdiy] DsPIC timer issue when used as DCO!

[Tom Wiltshire]

On 10 Dec 2009, at 21:00, karl dalen wrote:

>>> According to timer manual that seams to be the cause
>> of the problem,
>>> i.e no absolute jump to new timer count value as the
>> old 8253 could do?
>>
>> No, you can do that on dsPIC too. There's TMRx registers
>> that store the current timer count. You can set those to
>> whatever you like.
>> The tricky bit is the working out *what* the correct value
>> should be.
>
> ? So what is the real problem then? If you can set TMRx, OCx R/RS
> as you say i dont see why these wouldn't be used to avoid the glitch?
>
> How do we know that the OC registers emideately update timer count?
> We dont because they dont, becuse they are in toggle mode, OC  
> registers are usually used in PWM generation. Where in the timer  
> manual does it
> say timer count gets updated on a new reload of TMRx register?
> I cant find it!?

I think you're thinking about doing it a different way to how I was  
thinking about doing it!
Output compare (OC) is a separate feature, and I wouldn't have  
thought you needed it for generating DCO reset pulses (I didn't need  
it).

Looking through the chapter on it, I can see that it does look rather  
appealing for the job in hand, though - assuming it can be made to  
work with 32-bit counters.

If that's how DSI did it, then I think they missed this bit! -
"The user application must disable the associated timer when writing  
to the output compare control registers to avoid malfunctions."

> Whats the difference between PRx and TMRx in comparator toggle mode?

TMRx is the actual count, the number of master clock pulses that have  
arrived at the counter. PRx is the "Match" value. When TMRx matches  
PRx, the counter is reset (TMRx = 0), and an interrupt is generated.  
This *does* work with concatenated 32-bit counters.

The way I did it was to use the interrupt routine to then set a pin  
high to reset the ramp generator. Interrupt latency isn't much of an  
issue. It takes 5 cycles, which at the max clock of 40MHz is 125nS.  
Most analogue ramp resets are measured in uS, so you've got time to  
get your reset pulse out *and* get the kettle on before a full uSec  
has elapsed.

Dave, if you're reading this, feel free to send me a Prophet and some  
code, and I'll do my best to fix it for you!

T.