[sdiy] Tap Tempo LFO

[Tom Wiltshire]

On 9 Dec 2009, at 12:18, Antti Huovilainen wrote:

> On Tue, 8 Dec 2009, Eric Brombaugh wrote:
>
>> Using a general-purpose MCU to create a clock for a BBD is  
>> probably out of the question for most garden-variety processors.  
>> While a lot of them have divider-based timing generators built-in,  
>> the high-frequency resolution is probably not adequate to support  
>> decent timing & frequency control at the rates needed to clock a BBD.
>
> Here I disagree. A simple VCO is not that hard to do if you stick  
> to V/Hz and disregard linearity. A PLL would also be dead simple to  
> do, too.
>
> With the VCO you need to build a calibration table and/or adjust  
> the frequency on the fly, but that's hardly rocket science.
>
> Antti

Maybe I'm misunderstanding you, Antti, but can you explain further,  
because I can't see how you can make this work with just a uP. With a  
PLL too, fine.

For example, the PIC 16Fs that I've been using have a max clock rate  
of 20MHz, and the instruction cycle is 1/4 of that, only 5MHz. This  
means that if you use the chip to generate a 200KHz BBD clock, you've  
only got 100 clock cycles per BBD clock, and only 25 instruction  
cycles. That's nothing like enough to be able to modulate the delay  
time smoothly. Like Eric said, the high-frequency resolution is *not*  
adequate to support decent timing & frequency control at the rates  
needed.

You might be able to make the uP generate one particular clock  
frequency, but what's the use of that? We want to be able to (at  
least) alter the delay time, and ideally I want to modulate it using  
software LFOs or other modulation generators. After all, that's the  
fun bit!

Or do you think of "Intel Core Duo" when someone says "Garden variety  
processors" (not entirely unreasonable these days), in which case  
we're talking at cross-purposes...

T.