[sdiy] More VCO fun

[ASSI]

On Tuesday 08 December 2009, David G. Dixon wrote:
> I just simulated your solution, and it is WAY BETTER!  Resetting is
> occurring in just about exactly one microsecond.  My feeble,
>  inappropriate JFET is now truly happy!  And, the kludge will be
>  incredibly easy on my existing layout, which is a bonus.

I think R22 in Oren's schematic should be connected to GND, not +15V.  
The way it is wired now the diode doesn't match up with his 
description.  You can shed another resistor by using my original 
suggestion:

JFET Gate o--------+-----/\/\/\-----o +15V
                   |
Comp Out  o--------+-----|>|--------o GND

You can use a normal low-Vf diode if you don't have a Schottky  ...and 
if you keep the low-cutoff transistor you might still want to connect 
the emitter of the output stage to something a little bit higher than 
-15V.  A Zener between pin 3 and 6 should do that, the current is 
already limited by the resistor going to +15V.



Achim.
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