[sdiy] More VCO fun

[David G. Dixon]

...and the winner is...

Oren Leavitt!!!  (and the crowd goes wild as the camera pans to a tearful
synth-diyer standing on the podium with hand on heart underneath an enormous
flag as the anthem is played in cheesy Casiotone monophony...)

I just simulated your solution, and it is WAY BETTER!  Resetting is
occurring in just about exactly one microsecond.  My feeble, inappropriate
JFET is now truly happy!  And, the kludge will be incredibly easy on my
existing layout, which is a bonus.

BTW, the comparator is switching almost infinitely faster compared to the
draining of the cap through the JFET, so I don't think that the choice of
comparator is material.


> I have done a similar work-around for the JFET gate capcitance issue:
> 
> http://www.analogcreations.com/images/vco_osc.gif
> 
> By pulling the LM311 up to the V+ rail and adding a diode to limit the
> gate "off" voltage to just a diode drop in the V+ direction.
> Reset times were well less than a micro-second even with the 4.3 nF cap
> in the schematic.
> I'd be curious to see what results you get in your simulation. This has
> worked very well in practice, in a quartet of oscillators I built around
> 2001.
> I like Achim's idea of using a push-pull device like the LM319 to drive
> the JFET switch.