[sdiy] More VCO fun

[Oren Leavitt]

David G. Dixon wrote:
>>[off-list]
> 
> 
> Actually, it wasn't, but that's OK!
> 
> I've simulated your idea (or, a variation of it, at least) and I believe
> that you are correct.  My solution was to put a 10V zener between the JFET
> gate and the comparator output.  This holds the gate at -5V when the
> comparator output is low at -15V.  And yes, indeed, the response is faster.
> Putting a small (<100pF) cap across the zener also speeds up the response.
> 
> I will alter my circuit accordingly, and then it will be perfect!  :)
> 
> Thanks, Achim!
> 
> 

David,
I have done a similar work-around for the JFET gate capcitance issue:

http://www.analogcreations.com/images/vco_osc.gif

By pulling the LM311 up to the V+ rail and adding a diode to limit the 
gate "off" voltage to just a diode drop in the V+ direction.
Reset times were well less than a micro-second even with the 4.3 nF cap 
in the schematic.
I'd be curious to see what results you get in your simulation. This has 
worked very well in practice, in a quartet of oscillators I built around 
2001.
I like Achim's idea of using a push-pull device like the LM319 to drive 
the JFET switch.

- Oren

> 
>>Hi David,
>>
>>On Thursday 03 December 2009, David G. Dixon wrote:
>>
>>>One thing I am finding with this updated circuit is that I need an
>>> even bigger reset RC to ground the integrator cap.  I'm up to
>>> 3.3us now (33pF * 100k) and I'm still only getting to within about
>>> 100mV of ground (resetting a 1nF cap from +5V).  I am thinking of
>>> going to 47pF, but I know this will wreak havoc with high
>>> frequency tracking.  It also defeats the purpose of having a
>>> high-speed comparator (although LM311 isn't exactly "high-speed"
>>> as comparators go...).  Of course, I'm using 2N5485 (still)
>>> instead of 2N4391, although my simulations all show that this
>>> should actually work better.
>>
>>I'm assuming your circuit is very similar to Ian's, as I'm really
>>commenting on that (I don't think I ever saw a link to your circuit).
>>Both the switch itself and the control are not ideal for what you want
>>to achieve.  The JFET used is a depletion transistor, which means it
>>is switched on when V_GS becomes zero (or indeed very slightly
>>positive, but not so much that the G-S-diode opens).  After reset, the
>>comparator is held at -12V (since both pin 3 and 6 are tied to this).
>>This is only good if you are using a transistor with a high cutoff
>>voltage that actually needs such a high V_GS to be switched off.  The
>>one you are actually using has much lower cutoff and should not be
>>driven so deep into depletion.
>>
>>During reset the gate capacitance will be discharged through R23-R24
>>to ground only.  Again, if you have a transistor with a high cutoff
>>voltage this is probably going to work out, otherwise the transistor
>>may never actually switch fully on until quite some time has passed
>>(the gate RC is about 10-15ns here and is getting larger as zero V_GS
>>is approached).  That is if there wasn't the "timing" cap, which
>>increases the effective RC by about 3 times.  The simulation should
>>show this... anyway, for a JFET with low cutoff you need to come much
>>closer to zero V_GS to really switch them on and I suspect you never
>>really do that before the comparator calls it a day and pulls down
>>again.
>>
>>It would be much better to use a comparator that has a push-pull
>>output stage or follow up with one.  Alternatively, if you want to
>>stay with that circuit feed some ~mA current into the output of the
>>LM319 via a resistor from +12V and put a Schottky diode from output to
>>ground.  This way the comparator will switch faster, the JFET will
>>open much better and you should be able to reset in quite a bit under
>>1µs.
>>
>>
>>Regards,
>>Achim.
>>--
>>+<[Q+ Matrix-12 WAVE#46+305 Neuron microQkb Andromeda XTk]>+
>>
>>Wavetables for the Terratec KOMPLEXER:
>>http://Synth.Stromeko.net/Downloads.html#KomplexerWaves
>>
>>
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