[sdiy] More VCO fun

[David G. Dixon]

> >Right.  I had actually read that paragraph quite a while ago and had
> >forgotten.  I wish I would have remembered at about 11 o'clock lastnight,
> >when I was freaking out about how to fix my VCO.  Actually, about two
> hours
> >into the ordeal, I had the idea that temperature was affecting the
> >on-resistance, and that's when I decided to fix the reset timing
> resistor.
> 
> Yeah, that had me stumped for quite a while, too.
> 
> 
> >One thing I am finding with this updated circuit is that I need an even
> >bigger reset RC to ground the integrator cap.  I'm up to 3.3us now (33pF
> *
> >100k) and I'm still only getting to within about 100mV of ground
> (resetting
> >a 1nF cap from +5V).  I am thinking of going to 47pF, but I know this
> will
> >wreak havoc with high frequency tracking.  It also defeats the purpose of
> >having a high-speed comparator (although LM311 isn't exactly "high-speed"
> as
> >comparators go...).
> 
> Isn't it just that you need extra time to make up for the slew time that
> you had with the opamp?  Still, it's an unusually long time
> constant.  Remind me, what value is your integrating cap?

Only 1nF, with a ramp height of 5V.  It should drain out in a jiffy!

By the way, subsequent simulations suggest something new (or at least not
shown in your schematic): Putting a small cap (say, 47pF) between the
comparator inputs helps dramatically to bring the reset right down to ground
at significantly lower RC constants, and just generally cleans up the saw
reset response.  I'm definitely going to add said cap to my circuit as soon
as I get home tonight to confirm.


> >However, r_DS also
> >decreases with increasing V_GS(off), such that r_DS is about 90ohms at
> >V_GS(off) of -8.0V at 25degC.  Does this mean that holding the gate at
> lower
> >voltages when off gives lower channel resistances when on?
> 
> No.  (The device has no way of knowing where you had been holding the gate
> previously.)  V_GS(off) is the pinchoff voltage of the device (a device
> parameter), not the voltage you are holding the gate at.

That's what I suspected.  I found some handy-dandy little test circuits in
an application note on JFETs (Motorola AN211A) for measuring the forward
transadmittance y_fs (essentially the same as the transconductance g_m) and
some other things, which I might throw together on breadboard for selecting
the best JFETs.  Incidentally, this value (which the application note
suggests is THE figure of merit for JFETs) is essentially the same for
2N5485 (3.5mS (min) to 7mS (max) @ V_DS = 15V, I_S = 1mA) and 2N4391 (6 mS
(typ) @ V_DS = 20V, I_S = 1mA).


> >Also, the data
> >table says that 2N5485 has a minimum V_GS(off) of -0.5V and a maximum of
> >-4.0V.  From the chart, this would imply about a factor-of-four
> variability
> >in the on-resistance.  Am I interpreting this correctly?
> 
> Probably. Just make sure to check if the curve is for a whole family of
> devices, in which case you have to use just the part of the curve that
> pertains to your particular device.  What values is your simulator using
> for these parameters?
> 
> For the 2N4391 device I use, the V_GS(off) ranges from -4V to -10V and the
> corresponding change in R_DS is about 50%.
> 
> Notice also, while we are at it, that the saturated drain current
> increases
> with increasing pinchoff voltage.

Yes, JFETs are not the most consistent little bastards, are they?  I must've
stuck a relatively crummy one in my circuit lastnight.