[sdiy] More VCO fun

[David G. Dixon]

> >Concerning the JFET temperature sensitivity (which caused the pitch to
> >increase by several semitones upon touching the JFET with my fingertip),
> >this really had me stymied, since my other circuits don't show this
> >sensitivity. ............
> 
> >Has anyone else here ever observed these problems with
> >JFET reset time constants in sawcore VCOs?
> 
> Yes:
> http://home.comcast.net/~ijfritz/sy_cir2.htm
> Fifth paragraph.
> 
> Ian

Right.  I had actually read that paragraph quite a while ago and had
forgotten.  I wish I would have remembered at about 11 o'clock lastnight,
when I was freaking out about how to fix my VCO.  Actually, about two hours
into the ordeal, I had the idea that temperature was affecting the
on-resistance, and that's when I decided to fix the reset timing resistor.

One thing I am finding with this updated circuit is that I need an even
bigger reset RC to ground the integrator cap.  I'm up to 3.3us now (33pF *
100k) and I'm still only getting to within about 100mV of ground (resetting
a 1nF cap from +5V).  I am thinking of going to 47pF, but I know this will
wreak havoc with high frequency tracking.  It also defeats the purpose of
having a high-speed comparator (although LM311 isn't exactly "high-speed" as
comparators go...).  Of course, I'm using 2N5485 (still) instead of 2N4391,
although my simulations all show that this should actually work better.

One thing about 2N5485 (and, presumably, all similar JFET switches) which
I'd like to have clarified:  In the datasheet, there is a chart (top right
on page 3) which plots channel resistance vs temperature at four values of
V_GS(off), with V_DS = 100mV and V_GS = 0V.  According to the chart, r_DS
increases (more or less) exponentially with increasing temperature, thus
explaining our observations at incomplete reset.  However, r_DS also
decreases with increasing V_GS(off), such that r_DS is about 90ohms at
V_GS(off) of -8.0V at 25degC.  Does this mean that holding the gate at lower
voltages when off gives lower channel resistances when on?  If so, then
holding the JFET off with a comparator (at -15V) would ensure the lowest
on-resistance (about 60ohms at 25degC by extrapolation).  Also, the data
table says that 2N5485 has a minimum V_GS(off) of -0.5V and a maximum of
-4.0V.  From the chart, this would imply about a factor-of-four variability
in the on-resistance.  Am I interpreting this correctly?