[sdiy] Divide down question

[Dave Manley]

Cheater was asking for the verilog.  Here's one simple implementation. 
I'm not claiming it is the smallest, or the fastest, or the best in any 
way, this is just a simple, naive, 10 minute implementation. It gets 
close to 50% duty cycle, on the odd divisors.  To stick it in an FPGA or 
CPLD is trivial at this point, well the whole thing is trivial.

// simple parameterized divider
module togDiv(rst, clk, f);

input rst;
input clk;
output f;

parameter MAX = 230;
parameter MID = (MAX-1)/2;

reg [8:0] div;
reg       f;

always @ (posedge rst or posedge clk) begin
         if (rst) begin
             div <= 9'b0;
             f <= 1'b0;
         end else begin
             if (div == MAX-1) begin
                 div <= 9'b0;
                 f <= 1'b0;
             end
             else begin
                 div <= div + 9'b1;
                 if (div == MID)
                     f <= 1'b1;
             end
         end
end
endmodule

// now instantiate 12 of the dividers with the right divisor values
module tog(rst, clk, fout);

input rst;
input clk;
output [11:0] fout;

     togDiv #(.MAX(9'd478)) divC  (rst, clk, fout[0]);
     togDiv #(.MAX(9'd451)) divCs (rst, clk, fout[1]);
     togDiv #(.MAX(9'd426)) divD  (rst, clk, fout[2]);
     togDiv #(.MAX(9'd402)) divDs (rst, clk, fout[3]);
     togDiv #(.MAX(9'd379)) divE  (rst, clk, fout[4]);
     togDiv #(.MAX(9'd358)) divF  (rst, clk, fout[5]);
     togDiv #(.MAX(9'd338)) divFs (rst, clk, fout[6]);
     togDiv #(.MAX(9'd319)) divG  (rst, clk, fout[7]);
     togDiv #(.MAX(9'd301)) divGs (rst, clk, fout[8]);
     togDiv #(.MAX(9'd284)) divA  (rst, clk, fout[9]);
     togDiv #(.MAX(9'd268)) divAs (rst, clk, fout[10]);
     togDiv #(.MAX(9'd253)) divB  (rst, clk, fout[11]);

endmodule

That's it.

-Dave