[sdiy] Divide down question

[Tom Wiltshire]

On 25 Aug 2009, at 20:35, Scott Gravenhorst wrote:

> Tom Wiltshire <tom at electricdruid.net> wrote:
>>
>> On 25 Aug 2009, at 15:09, cheater cheater wrote:
>>
>>> Actually, couldn't you do a big part of square-based divide down
>>> topology in FPGA?
>>
>> Yes. Wasn't someone on this list doing a top-octave chip on an FPGA?
>> That's the hard part! The rows of flip-flops would be a good
>> "beginner's FGPA project" I'd have thought!
>>
>> T.
>
> I would think that an FPGA would be overkill for a TOG.  Moderate  
> sized ones have
> thousands of flipflops inside.  Heck, you can cram a whole  
> polysynth in an FPGA.
>
> A CPLD, on the other hand would be more of a challenge and unlike  
> an FPGA (most FPGAs
> are static RAM based), they retain their programming.

It was Tim Ressel doing the TOG design, and you're quite right, Scott  
- he _is_ using a CPLD.

T.