[sdiy] Divide down question

[Scott Gravenhorst]

Tom Wiltshire <tom at electricdruid.net> wrote:
>
>On 25 Aug 2009, at 15:09, cheater cheater wrote:
>
>> What about this:
>> start out with a normal square divide down, and then when you're e.g.
>> playing C1, then actually what is output is:
>> C1+ 1/2 C2 + 1/4 C3 + 1/8 C4
>>
>> Each of the higher tones would have to go through a latch. That latch
>> would only let through one pulse of C2, C3, etc, but it would be reset
>> on C1's rising slope. Maybe this could be a little bit difficult,
>> maybe not.
>
>Actually you don't need the latches. You're dead right with the rest  
>of it; C1+ 1/2 C2 + 1/4 C3 + 1/8 C4 + etc gives you a steppy saw. Try  
>it on graph paper, graphics calculator, or maths package (in  
>ascending order of techno-overkill). Since it's a bright buzzy sound  
>with even as well as odd harmonics, it actually sounds pretty much  
>like a saw even with fairly few steps. A good substitute, anyway,  
>even if not enough for perfectionists.
>
>> Actually, couldn't you do a big part of square-based divide down
>> topology in FPGA?
>
>Yes. Wasn't someone on this list doing a top-octave chip on an FPGA?  
>That's the hard part! The rows of flip-flops would be a good  
>"beginner's FGPA project" I'd have thought!
>
>T.

I would think that an FPGA would be overkill for a TOG.  Moderate sized ones have
thousands of flipflops inside.  Heck, you can cram a whole polysynth in an FPGA.

A CPLD, on the other hand would be more of a challenge and unlike an FPGA (most FPGAs
are static RAM based), they retain their programming.


-- ScottG
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-- Scott Gravenhorst
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