[sdiy] Reducing maximum current through analog switches in ASM-2 ADSR

[Tom Wiltshire]

Simon,

On 23 Nov 2008, at 20:16, Simon Brouwer wrote:
> What do you guys think? The minimum attack time would become about  
> 3 to 4 ms. Is that something to be content with that or should I  
> aim for a shorter attack time?

3 to 4 mS is still a reasonably fast attack. For really snappy  
envelopes, you need to be closer to 1 mS - think Minimoog, Sequential  
ProOne, SH101. But then again, lots of famous polysynths from the  
early era of microprocessor-based envelopes couldn't manage times  
anywhere near that short (Oberheim Xpander only updated the envelopes  
every 10mS, and the Waldorf Wave is notoriously sluggish too).

Do you really need to reduce the current so much? Is the chip  
actually in any realistic danger?
I'd have thought that although the peak current might exceed the  
absolute maximum rating, if this is done briefly (say for 1mS!) it  
might not cause any permanent damage. As the capacitor charges, the  
voltage drop across reduces, and the current drops correspondingly.  
Hence the period when this excessive current flows is actually very  
short.

Have you worked out roughly what the *average* current through the  
switch would be during the attack curve?

Alternatively, is there another version of the 4053 that you could  
use that has a higher current rating without increasing the on  
resistance?

Regards,
Tom