[sdiy] Gate input protection

[Seb Francis]

Actually getting on with the schematic input of the digi-module tonight 
... :)

A quick advice request:

The digital inputs of the dsPIC don't want voltages outside the 0V to 
3.3V range, with low/high levels being:
<0.66V = low
 >2.64V = high

So there needs to be some kind of buffer to accept gate signals from the 
'outside' world which could be anything from say -15V to 15V.  I'd like 
to keep it minimal component count and my 2 thoughts so far are as follows:

http://burnit.co.uk/sdiy/stuff/gate-buffer.png
(my ASCII art wasn't good enough to include the diagram in the actual 
email :)

The first option looks an elegant solution, but I'm not sure it's safe 
if a negative gate signal would be present.  Then the forward voltage 
across the zener (~1V) would allow -1V at the dsPIC input.  Or is the 
100K resistor enough to make this ok?  Is there a simple way to add 
protection for -ve gate voltages?

The 2nd option I think is ok, although higher component count than I'd 
prefer.  Am I right in thinking that I must have D2 to protect the 
transistor against high gate voltages?  (I'm a bit confused because of 
the transistor datasheets I've looked at some quote the max Emitter-Base 
voltage as +ve and others as -ve.)  And what happens if the gate input 
is negative, can the output get pulled negative?  Hmm, showing my 
transistor ignorance here .. must be too young, I grew up on ICs ;)

TIA,
Seb