[sdiy] dsPIC33 question..

[Eric Brombaugh]

On 13 November 2008, Seb Francis wrote:
> This looks like a neat little SRAM chip.  And the dsPIC can use DMA
> for SPI.  But unfortunately 32kByte isn't going to be anywhere near
> enough for a decent delay time.  (Actually I think you can get PICs
> with 32kByte of RAM built in anyway).

Someone please correct me if I'm wrong, but I don't believe that SPI DMA 
is particularly useful. The problem is that (at least as I have found) 
the dsPIC SPI port doesn't automatically control the Chip Select line in 
master mode - you need to toggle that bit with firmware instructions. 
That rules out using DMA on the SPI port to handle anything except long 
sequential SPI transfers where the CS line is static.

Since typical audio delay applications are going to require multiple 
interleaved read/write RAM accesses, you'll have to manage SPI RAM at a 
per-transaction basis. DMA would work, but setup/teardown overhead isn't 
going to be worth it for two-byte transfers.

ASSI wrote:
> That's why I said you need to gang them.  SI/SO goes to all of them in 
> parallel and /CS selects whichever you are going to use (SO is 
> tristate until the device is selected and gets a command to output 
> something and an unselected device ignores everything coming in on 
> SI).

For ~1.5s of 44.1kHz 1 channel audio you'll want ~128kx8 of SRAM, or 4 
of these babies @ $2/ea, plus extra board space & a decoder. That's $8+ 
in small qty. You can get 128kx8 parallel-access SRAM in SMD packages 
for ~$3 in small qty. If you've got an MCU with sufficient I/O you're 
better off going parallel.

> Ramtron has an FRAM with 256kx8 organization and SPI interface, but 
> I'm sure this would be more expensive than eight SPI SRAM and perhaps 
> a 3-to-8 decoder.

Those aren't bad - the 256kx8 parts run about $26/ea in small qty, so as 
you suspected they're about 1.5x more costly than equivalent SPI SRAM. 
Interesting thing is that you could save samples in them even when power 
is off.

Eric