[sdiy] Shift register sequence period

[Tim Stinchcombe]

Hi Neil,

> 1/ I think the start circuit is upside down - pin 13 of the 4030  
> should start HIGH (giving you an inverter) to overcome the all-zeros  
> startup state.  As is shown in the schematic at the start 
> there is no  
> inverter and so the all-zeros state is maintained.  Its only 
> when the  
> 0u47 cap has charged up does it get out of the all-zeros state.

*Because* of the inverting action, I don't think the circuit needs any kind
of 'kickstart' - there is nothing like that in either the Doepfer module
(and it works all the same!) or the Marston book I mentioned. For all I know
it could well generate a de Bruijn sequence, in which the all 0 case *is*
allowed of cause...

> 2/ Looking on the 'net for 18-stage maximal length tables I 
> don't see  
> anything that corresponds to this 3-tap design.  For maximal length  
> there is a single 2-tap and many 4-tap choices (some of which can be  
> implemented with the 4006), but nothing for 3-tap.

...which is why I don't expect to see it in any kind of table for maximal
length sequences - I don't think it can possibly be one!

Cheers,
	Tim
__________________________________________________________
Tim Stinchcombe 

Cheltenham, Glos, UK
email: tim102 at tstinchcombe.freeserve.co.uk