[sdiy] linearizing a JFET used as voltage controlled resistor.

[Dave Manley]

ASSI wrote:
> On Freitag 02 Mai 2008, Dave Manley wrote:
>>
>> http://www.vishay.com/docs/70598/70598.pdf
> 
> Two comments: 
> 
> 1) The App note still beats around the bush with the principle of the 
> linearization.  What it should just have plainly said is that you need 
> to add V_DS/2 onto V_GS for obtaining the largest dynamic range.  With 
> this in mind you can sometimes find different ways to linearize the 
> JFET without mucking about with extra resistors.

That is a simpler way of stating it.

> 2) Figure 15 has the polarity of the control voltage reversed.

Also Figure 6 has two errors - the equation below the figure is 
incorrect (see equation (3) instead), and VGS is incorrectly labeled VGG.

Overall, the app note is a good reference for someone unfamiliar with 
the technique.

-Dave