[sdiy] linearizing a JFET used as voltage controlled resistor.

[ASSI]

On Freitag 02 Mai 2008, Dave Manley wrote:
> Probably basic stuff to some of you, but I'm more of a digital guy
> than analog. This app note gives the basics on using JFETs as voltage
> controlled resistors - including a clear description of how to
> linearize the response.
>
> http://www.vishay.com/docs/70598/70598.pdf

Two comments: 

1) The App note still beats around the bush with the principle of the 
linearization.  What it should just have plainly said is that you need 
to add V_DS/2 onto V_GS for obtaining the largest dynamic range.  With 
this in mind you can sometimes find different ways to linearize the 
JFET without mucking about with extra resistors.

2) Figure 15 has the polarity of the control voltage reversed.


Achim.
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