[sdiy] Top Octave Generator (was Chinese MG-1s??!?)

[Phillip Harbison]

Veronica Merryfield wrote:
> A different thought, this would need 12 9bit counters and 12 9bit 
> compare logic blocks - that ought to fit in a small CPLD that cost
> a few bucks and the programming tools are free.

You could avoid the comparators by running the device at twice
the TOG master frequency and preload the counters with the 9-bit
divisors. Every time they count down to zero, toggle the output
of an additional flip-flop and reload the divisor. You still
need to compare for zero but that is a 9-input NOR gate rather
than a true 9-bit comparator.

I still think your other (CPU-based) idea would work. What you
are describing is what we call a "callout queue" in the kernel
world. Whenever you want to have a thread delay for N ticks of
the clock, you scan the list looking for an event with a count
greater than your desired count. Each time you pass over an
event you subtract its count. If the next event is greater than
your event, you insert in front of it and subtract your count
from that event's count. So if you had a chain of events like
this:  A(10)->B(15)->C(10)->D(20)->null then you would have
the follow event delays:
   A: 10
   B: 25
   C: 35
   D: 55

In a case where the CPU is not particularly fast, the code that
processes the callout queue could probably adjust for the time
it takes to run and if the next event is Real Soon then just go
ahead and process that event.

In this case an event requires the toggling of one or more of
the 12 outputs so processing the event queue can be as simple
as exclusive-ORing a 12-bit event mask and the current 12-bit
output register. You could possibly even add a bit of jitter
to the outputs by shaving off a clock or three now and then,
especially if there is an event in the queue that is already
close to the time delay you need.

-- 
Phil Harbison
http://www.xavax.com/