[sdiy] Simple VCA?

ASSI Stromeko at nexgo.de
Sat May 3 00:49:28 CEST 2008


On Samstag 12 April 2008, Roy J. Tellason wrote:
> It's a very simple circuit,  really.  An op amp inverting amplifier, 
> one resistor going from the non-inverting input to ground,  one input
> resistor, and one feedback resistor.  And,  a JFET connected between
> the two input terminals with the gate lead labeled as being the gain
> input.
>
> The caption for this reads "VOLTAGE-CONTROLLED GAIN -- 2N5457 FET
> acts as voltage-variable resistor between differential input terminals
> of opamp. Resistance variation is linear with voltage over several
> decades of resistance, to give excellent electronic gain control.
> Values of resistors depend on opamp used."  --"FET Databook",
> National Semiconductor, 1977, p. 6-26 -- 6-36.
>
> Comments on this?  Could that be done that simply?  Or what am I
> missing here?

Dave Manley linking to the Vishay app-note on JFET-VCR basics prompted 
me to revisit this circuit. (I hope I didn't goof up, it's been a long 
day...)

If this circuit works, then the V_DS of the JFET must be small 
and hence it presents a linear resistance which can be controlled by 
the Gate-Source voltage.  The resistance variation of the JFET is 
reciprocally linear with the negative CV because the drain current 
would be linear with -CV to first order (resitive region of the JFET), 
lowest resistance is with 0V at the gate and goes to (ideally) infinity 
when approaching the threshold voltage.  The circuit as drawn by Scott 
(thanks for the ASCII art) defies standard analysis because 
interpretation as either inverting or non-inverting amplifier leads 
astray.  But the operative word above is "between differential inputs" 
so I'd like to think of the circuit in this manner:

#                                 FB ?
# 
#                     +---------/\/\/\/---+
#             510R    |                   |
#                     |     |\            |
#  +IN/2 o--/\/\/\/---*-----|-\           |
#                     |     |  \          |
#                     |     |   \         |   
#                   |-+     |    \        |    OUT
#                   |       |     >-------*----->
#  -CV   o--------->|-+     |    /     
#                     |     |   /      
#                     |     |  /	      
#  -IN/2 o--/\/\/\/---*-----|+/	      
#                           |/  	      
#             510R     

It can now be seen that the (-) node must not be a virtual ground as it 
were in an inverting amplifier.  Let's for the moment ignore FB and 
pretend we have a bog standard differential amplifier.  The voltage 
developing across the differential inputs is indeed proportional to the 
negative CV - just insert the expression for the R_DS into the voltage 
divider equation.  It can indeed be controlled over several decades, 
three or four should be quite possible depending on the choice of V_DS, 
the lower the better.  By splitting the divider resistors this circuit 
also linearizes the JFET response by coupling V_DS/2 onto the gate if 
you reference the CV to GND.  The opamp should have zero offset and 
very low input current for this circuit to work well.

The original single-ended topology is restored by adding a common mode 
voltage of IN/2 to all inputs, which is rejected by the differential 
amp so the output is still single-ended.  The CV however now needs to 
be offset by IN/2, which is inconvenient, but maybe less so than 
symmetrizing the signal.  The JFET could be replaced by a MOSFET, but 
these would be noisier, have significantly smaller gm and the control 
law isn't as convenient as the CV needs to be offset by the threshold 
voltage (OK, in the single ended version it's just another offset to 
deal with).  In all cases the gain is quite temperature dependent and 
compensating for this would probably be too much trouble.  Also, no two 
JFETS are alike, so brace yourself for quite some parameter variation.

Now this feedback resistor still presents a real problem.  If it were 
connected as drawn, the circuit won't work and reverts to an inverting 
amplifier, nullifying any effect that the JFET might have had.  We 
would have to assume non-ideal behaviour of the op-amp, parasitic 
resitances somewhere in the circuit - or re-draw the circuit with a 
proper differential amp.

#                                                  R2
# 
#                                       +-------/\/\/\/---+
#             510R               R1     |                 |
#                                       |   |\            |
#  +IN   o--/\/\/\/---*---o---/\/\/\/---*---|-\           |
#                     |                     |  \          |
#                     |                     |   \         |   
#                   |-+                     |    \        |    OUT
#                   |                       |     >-------*----->
#  -CV   o--------->|-+                     |    /     
#  +IN/2              |                     |   /      
#                     |                     |  /	      
#   GND  o--/\/\/\/---*---o---/\/\/\/---*---|+/	      
#                                       |   |/  	      
#             510R               R1     |
#                                       |
#                    GND  o---/\/\/\/---+
#
#                                R2

The gain is now set by -R2/R1, the repetition of these at the positive 
input reduces drift by equalizing the input impedance.  With the proper 
choice of opamp you can maybe leave those two resistors out.  If 
however you get also rid of the 510R to ground, like Fig.12 in the 
Vishay/Siliconix AN105, you remove the JFET linearization - so don't do 
that.


Achim.
-- 
+<[Q+ Matrix-12 WAVE#46+305 Neuron microQkb Andromeda XTk]>+

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