[sdiy] New dsPIC chips with on-chip audio DACs

[Veronica Merryfield]

On 28-Mar-08, at 10:02 AM, Eric Brombaugh wrote:
> Veronica Merryfield wrote:
>> The synergy uses a phase cancellation technique for amplitude  
>> control to avoid a multiply which could either be used or if this  
>> device has a quick multiply, that could be used
>
> There's a single-cycle 16x16->32 multiply available (signed or  
> unsigned), and if your additive synthesis involves summing up lots  
> of waveforms there are two 40-bit MACs with options for truncation  
> or rounding on unload.
>
> BTW - what's the output sample rate on the Synergy? That will have a  
> significant effect on the number of oscillators you can do. I've  
> usually run sample rates > 100kHz and can still get several  
> interpolated wavetable oscillators running simultaneously.
>
The original synergy has a 31250hz cycle time (32 slots of 1us). My  
virtual beastie has a a couple of modes, one of which is 100%  
compatible. It is also 16bit. The 20MIPS is a guide in this mode. The  
original hardware did a number of things in parallel per 1us slot.


>> (I'm still looking at the instruction set and it is more or less an  
>> instruction per cycle but pipelined - there are instructions that  
>> add a cycle or two of delay though so it might end up being nearer  
>> a 20MIPS processor with real code than the 40MIPS they quote).
>
> Yes, branching and table lookup instructions take more than one  
> cycle, so the 40MIPS may be a bit optimistic. OTOH, when doing  
> repetitive computations like multiply-accumulate of several vectors  
> there are low-overhead repeat prefixes and auto-incrementing  
> prefetches that allow you to get a lot of stuff done simultaneously  
> and keep the pipelines full.
>
> Eric
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