[sdiy] Digital noise sources

[Magnus Danielson]

From: Dave Manley <dlmanley at sonic.net>
Subject: Re: [sdiy] Digital noise sources
Date: Sat, 14 Jun 2008 16:31:22 -0700
Message-ID: <485454CA.2060603 at sonic.net>

> Magnus Danielson wrote:
> > From: Dave Manley <dlmanley at sonic.net>
> >   
> >> For maximal length sequences:
> >>
> >> If the feedback is XOR, the initial state can be anything except all 0.
> >> If the feedback is XNOR, the initial state can be anything except all 1.
> >>
> >> A safe thing to do is to load a mixed value, since that will work with either feedback type.
> >>     
> >
> > Actually. Most designs uses XOR. When you don't have any other reasons, the
> > default is to initiate to all ones.
> >   
> The point is you need to look at the feedback and that it isn't safe to assume all-one, or all-zero is always the right answer.  If someone takes 'all-one' as a rule of thumb, they may end up confused with a 'dead' noise generator. 

Indeed, in the generic sense it is not safe to assume, but considering that
most designs actually uses XOR, you end up having the all-ones case. THAT was
my point.

Actually, it is not XNOR in itself but rather the inverse of feedback which is
critical. If the input is inverted so is the state of the shift register.
Anther aspect could be that the inversed outputs is being used.

Using non-prime factors causes there to be other short groups. Just to help
confusing things a bit.

If in doubt, just try initiate all-ones and all-zeros and see if any of those
will generate the expected length sequence or not.

> >> In general it is not safe to assume that logic is going to power up in a certain state (FPGAs are one exception).  There should be explicit reset logic that loads a valid state, and if you are really paranoid, you can add logic that detects any *invalid* states and force the shift register into a valid state.
> >>     
> >
> > Never assume reset-state. Always use explicit reset. FPGAs loads known state,
> > but since you want to reset again, you do explicit reset there too. There are
> > flip-flops which does not require resets, since whatevet their initial state
> > was, it will be clocked out anyways. Shift registers belongs to this group.
> > Removing explicit reset may result in more optimal "fit" into FPGAs while not
> > being a major risc (you must be aware of first bit being random and await it's
> > shift-out, which you may do most of the times).
> >   
> LOL.  I only mentioned FPGA, because if I didn't I figured someone would argue, "What about FPGAs they always power up in a known state!".  Also there are some designs that use the 'reload the configuration file' method on every reset.  Using that method, there's never an issue of removing reset logic.  I'm not *encouraging* it, just saying I've seen it done.

For FPGAs there is really two RESET signals, one for the chip hardware and one
for the soft chip. I was naturally talking about the needs for the soft reset.

Cheers,
Magnus