[sdiy] Digital noise sources

[Dave Manley]

Magnus Danielson wrote:
> From: Dave Manley <dlmanley at sonic.net>
>   
>> For maximal length sequences:
>>
>> If the feedback is XOR, the initial state can be anything except all 0.
>> If the feedback is XNOR, the initial state can be anything except all 1.
>>
>> A safe thing to do is to load a mixed value, since that will work with either feedback type.
>>     
>
> Actually. Most designs uses XOR. When you don't have any other reasons, the
> default is to initiate to all ones.
>   
The point is you need to look at the feedback and that it isn't safe to 
assume all-one, or all-zero is always the right answer.  If someone 
takes 'all-one' as a rule of thumb, they may end up confused with a 
'dead' noise generator. 

>> In general it is not safe to assume that logic is going to power up in a certain state (FPGAs are one exception).  There should be explicit reset logic that loads a valid state, and if you are really paranoid, you can add logic that detects any *invalid* states and force the shift register into a valid state.
>>     
>
> Never assume reset-state. Always use explicit reset. FPGAs loads known state,
> but since you want to reset again, you do explicit reset there too. There are
> flip-flops which does not require resets, since whatevet their initial state
> was, it will be clocked out anyways. Shift registers belongs to this group.
> Removing explicit reset may result in more optimal "fit" into FPGAs while not
> being a major risc (you must be aware of first bit being random and await it's
> shift-out, which you may do most of the times).
>   
LOL.  I only mentioned FPGA, because if I didn't I figured someone would 
argue, "What about FPGAs they always power up in a known state!".  Also 
there are some designs that use the 'reload the configuration file' 
method on every reset.  Using that method, there's never an issue of 
removing reset logic.  I'm not *encouraging* it, just saying I've seen 
it done.

-D