[sdiy] Digital noise sources

[Dave Manley]

Tom Arnold wrote:
> Something else I've been pondering.
> 
> I noticed in Tom Wiltshire's noise generator PIC that he preloads the shift
> registers with some random data.  I'm curious about something though...  In
> a "normal" logic based noise source, are we depending on the power-on state
> of the shift register to be random, or are we just loading it from 0 with
> the pattern generated from the XOR's?
> 

For maximal length sequences:

If the feedback is XOR, the initial state can be anything except all 0.
If the feedback is XNOR, the initial state can be anything except all 1.

A safe thing to do is to load a mixed value, since that will work with 
either feedback type.

In general it is not safe to assume that logic is going to power up in a 
certain state (FPGAs are one exception).  There should be explicit reset 
logic that loads a valid state, and if you are really paranoid, you can 
add logic that detects any *invalid* states and force the shift register 
into a valid state.

One circuit that was recently discussed here, had a XOR in the feedback 
with one input tied to the power on reset circuit.  This has the effect 
of removing an inversion when reset is de-asserted (asynchronously from 
the clock, which wasn't controlled by the reset).  This makes it very 
likely there will be a mix of ones and zeros in the shift register after 
reset.  Oddly enough for this circuit it didn't really matter, it wasn't 
maximal length and the all-zero and all-one states were both valid.

-Dave