[sdiy] Inifinity encoders

[Csaba Zvekan]

> I was referring to Manuels Schematic. Now looking at some  
> interesting designs from µCAapps.de .
>
> On Jul 9, 2008, at 4:42 PM, Samppa Tolvanen wrote:
>
>> and 74HC165 datasheet. Pin 1 /PL is brought low to "sample" state of
>> parallel input bits and then high (values are now on shift register).
>> Now these can be shifted out with clock signal. Pin 10 Ds is for
>> cascading and must be terminated at the end of the chain.
>
> In Manuels case I bring SH low (sample State)then high then clock  
> sixteen  times the  data in .I assume IC5 H first and IC1 A last ?
> I thing I'll brew something together ... I like this :)
>
> Thanks Samppa , Thanks Manuel
>
> Csaba
>