[sdiy] dsPICs with DACs: linearizing the 12 bit ADCs, external RAM?

[Robin Whittle]

Hi Eric,

That is great you got the chip and got it going.  I requested some
samples from Microchip but they were back-ordered and will probably
arrive in a month or two.

I did some audio work with a dsPIC30 a few years ago and found it to
be a really good device.  I used the Microchip MPLAB using assembly
code only, whith the IDC2 debugger/programmer.  The dsPIC33 series
are faster and have better DMA for peripherals.

I am really averse to surface mount and want to do fancy things such
as ADC, reverb and delay (requiring extra memory, perhaps) with DIP
components.  The 28 pin DIP devices:

  http://ww1.microchip.com/downloads/en/DeviceDoc/70292B.pdf

  dsPIC33FJ64GP802     64K FLASH } 16K RAM	
  dsPIC33FJ128GP802   128K FLASH }

are the ones I am keen to use.  There are no 40 pin DIP versions,
and I would be surprised if any emerge.


I am intrigued about the possibility of linearising the 12 bit ADC
in some way to be used as one or two audio inputs.  There would be
some basic limits of ADC noise, which might be overcome somewhat by
oversampling.

I was thinking of linearizing the ADC by techniques including these.
 This is for a single channel input, but in principle it might be
possible to do most of it for stereo inputs:

Get an inverting and non-inverting version of the audio input and
present them to two separate ADC input pins.  Then do two separate
conversions, invert one result and add it to the the other.  This
produces a 13 bit result and would reduce inherent non-linearity in
the ADC, the worst of which would probably be the midpoint MSB error
at 0111 1111 1111 to 1000 0000 0000.

Also, bias the voltages so the zero point of the signal is well
enough away from the mid-point of the ADC so this is only traversed
when the signal level is moderately high.

These two techniques could be used together.  To make the example
easy, let's assume the input range is 1 to 3 volts.

Take the normal audio in (after some diode-based clipping circuit so
we don't overdrive the ADC pins) and drive it into ADC input 0 with
a centre voltage of 1.9V.  So only when the audio input signal gets
to be more than 0.1 volts do we get any trouble from the MSB distortion.

Then invert the signal and send it to another ADC pin also biased at
1.9V.

Now we get a positive MSB distortion problem, divided by two, when
the signal goes 0.1 volts above centre voltage, and an inverted
version of the MSB distortion, divided by two, when the signal goes
0.1 volts below the centre voltage.

Also, we get partial clipping when the input signal goes beyond the
+/- 0.9 volt range, with 50% of the proper slope, until the signal
reaches +/- 1.1 volts, which is a flat slope - fully clipped.

Still, this is a 13 bit result from a 12 bit ADC.

To linearise it more, add a dither voltage, in effect exactly the
same voltage to both these ADC inputs.  Make it a substantial dither
voltage - enough to span at least one step of the 12 bit ADC range.

Maybe make it bigger, such as 4 steps, to help with larger
non-linearities than the basic 12 bit limit.

The beauty of this is that because we are subtracting one ADC result
from the other, the dither voltage should become inaudible.  The
trick would be to get the dither voltage exactly the same for both
samples, which must be done at different times since there is a
single 12 bit ADC.  Perhaps, with suitable RC filtering of the
dither signal, and with downsampling the ADC results, we don't need
to worry too much about the dither voltage changing from one sample
to the next.  Maybe this can be done with some kind of high-pass
filter on the dither circuit so most of its energy is above 20kHz
and so won't be audible.

Probably this dither could be added at the reference pin, or in the
AN1 pin, rather than mixing it into both the ADC input pins.  The
internal Sample and Hold amplifiers have an inverting and
non-inverting input, so we could use the inverting input for the
dither, such as via the AN1 pin.

Figure 16-1 in DS70183A has the block diagram of the ADC system:

  http://ww1.microchip.com/downloads/en/DeviceDoc/70183A.pdf

Dither might be produced by RC-filtering a digital output pin driven
 with some noise from a pseudo random number generator, such as the
Park-Miller-Carter algorithm (with dsPIC code):

  http://www.firstpr.com.au/dsp/rand31/

Then, oversample the audio.  Say we want 50kHz sampling, can we run
the above dual conversion approach with two samples with one dither
voltage per pair of conversions, at 100k pairs a second, or 200k?
The ADC runs up to 500k samples a second in 12 bit mode.  To the
extent we can oversample by a factor of 2 or 4, we add 1 or 2 bits
to the 13 bit resolution as part of the decimation process, in which
we run the samples through a FIR filter and down sample them.


I tried to figure out how to connect external RAM to one of these 28
pin DIP devices -  to do reverb, delays etc. beyond the limits of
the internal RAM.

My conclusion is that there is no 8 pin RAM chip (SPI interface) in
existence.  All those chips are for FLASH, EEPROM etc.

Static RAM involves 8 bit data busses and massses of address pins.
Maybe some port expanders such as the 28 pin DIP MCP23017 / MPC23S17
would work, but this is getting bulky and messy.

Old 4 bit wide DRAMs might be pressed into service, since they
multiplex their address lines 2 for 1, but these haven't been in
production for ten or fifteen years.  But even then, the biggest
device would be 256k bits, which is only 32k 16 bit words.

There seems to be no audio ADCs in a DIP package - and hardly any
(none?) 16 bit ADCs in a DIP package either.

An external audio ADC and/or DAC can be interfaced neatly to these
chips via the CODEC interface (Data Converter Interface).  The
Product Selector chart seems to be erroneous in stating that these
DAC chips do not have a Data Converter Interface.  These chips have
no dedicated pins for this function - the CODEC interface pins can
be made to appear on any of the Remappable Peripheral pins.


  - Robin             http://www.firstpr.com.au/rwi/dfish/