[sdiy] Digital 4 pole filter in an FPGA

[Jim Patchell]

Hope y'all aren't getting tired of these progress reports.

But it looks like I have got the basics of the four pole filter working 
(at least in the simulator).  It is going to take a bit more testing to 
verify that all of the data is going where and when it is supposed to...

The filter has a four clock pipe delay through it...i.e. it takes four 
clock cycles to complete one sample...but since it is pipelined...it 
only takes 512 clocks to complete all 512 filters...

One of the things I need to verify yet is that the resonance control 
works as it should.

Now, also to give you an idea of exactly what I am doing, this is 
basically the same kind of filter you would make with an 
SSM2040...without, unfortunately, the non-linear distortion that is 
inherent in the SSM2040.  I am not sure if I will be able to add a 
non-linearity in the filter loop or not.  That may be some future 
experiment.

Anyway...it is sure looking promising.

-Jim
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