[sdiy] Teaching our Senior Design class this Fall

[Scott Gravenhorst]

>"Who has the patience to grind out a divider chain design where some of the
>divisors are an odd number ... but a 50% duty cycle output is required?"

Interesting problem - as Paul Perry said, it can be easy _if_ the required divide ratio
is an even number, one can do what one wants until the end of the chain where a toggle
is placed which forces an 50% duty cycle.

I had done this once with a need to divide by 3 while maintaining a 50% duty cycle
output.  I used 3 CMOS JK flip-flops and a NOR gate.  One must be careful to design for
a glitch free output.  

I don't know the "proper" (as in taught in a school) way to design this, I did it by
banging my head against the wall with hand drawn timing charts for a day and a half
until I got what I wanted.


-- ScottG
______________________________________________________________
-- Scott Gravenhorst
-- GateManPoly - FPGA-based Polyphonic MIDI LA/FM Synthesizer
-- GateMan-III - FPGA-based Monophonic MIDI LA/FM Synthesizer
-- PolyDaWG/8 - FPGA-based 8 Voice Polyphonic MIDI Synthesizer
-- FatMan: home1.gte.net/res0658s/fatman/
-- NonFatMan: home1.gte.net/res0658s/electronics/
-- When the going gets tough, the tough use the command line.