[sdiy] dspic VCDO

[ryan williams]

i'm not actually overclocking. i"m just running the oscillator clock
itself a bit fast. I would expect that if you keep it within spec, it
shouldn't have any significantly reduced life expectancy?

it won't run any slower. i have no time left between interrupts.
reducing sample rates is the only way i know to slow it down and then
performance may suffer. I at least don't want to slow down the output
sample rate and that is the only one that would save much on clock
speed since it uses nearly half the processor time.

-Ryan

On Sun, Aug 17, 2008 at 7:07 AM, Csaba Zvekan <czvekan at gmail.com> wrote:
> Ryan,
>
> I think life expectancy and performance may also be an issue. Of course you
> can over clock your MCU and at first every thing seems to work fine . But
> the problem arises over time when the part is in stress for a longer period.
> Overheating is the main cause of all our electronic problems. And this can
> cause timing instabilities as well.
> But my question is : could you run your design at  µC 8XPLL @10MHz running
> at 80MHz ? Or would some parts of the routines be too slow ?
> What routine exactly requires the high speed clock?
> You would save a lot more current plus it's much safer for the part.
>
>
> Csaba
>
> On Aug 16, 2008, at 10:30 PM, ryan williams wrote:
>
>> thanks,
>>
>> the 30MHz crystal was actually a mistake. i didn't realize it was out
>> of range. but it isn't as far out of range as you thought. this dspic
>> has a HS xtal mode which handles 10-25MHz with PLL. it is actually
>> xtal/2 with PLL * 8. now the 15MHz xtal version of my crystal isn't in
>> stock anywhere so I haven't replaced it.
>>
>> yes, now that its done and i see the power is much higher than i
>> thought it would be. I didn't consider this much because i've never
>> used a uC at these speeds. i'll have to look at the 33F series, but a
>> quick glance at shows me that i'd need a new PCB layout to try one
>> out. and some redesign since it runs at 3.3V. I'm actually considering
>> now to use the NXP LPC ARM chips. that is what i use at work and it
>> should get the current draw down to 30-40mA.
>>
>> if/when I make another one, I want to have waveform banks with VC
>> control over waveform. I have at least proven the concept to myself:
>> good 1V/Oct with audio rate CV.
>>
>> On Sat, Aug 16, 2008 at 5:57 AM, Csaba Zvekan <czvekan at gmail.com> wrote:
>>>
>>> Hi Ryan,
>>>
>>> Great work on your VCDO . I was wondering why you used a 30MHz crystal in
>>> your design with PLL ? I thought that 4-10MHz was the maximum clock
>>> allowed
>>> .  Do you really  need the 4x PLL to get the 120MHz?
>>> I don't think I need to tell you that the slower you clock the less
>>> current
>>> it's being consumed.
>>> But also have you considered the dsPIC33Fxxxx series with nanowatt
>>> technology ?
>>>
>>> Csaba
>>>
>>> On Aug 15, 2008, at 8:26 PM, ryan williams wrote:
>>>
>>>> hi all,
>>>>
>>>> i built a new module a VCDO programmed in a dspic w/16bit ADC. exp
>>>> conversion is done with a lookup table. 24bit tuning word and a 32bit
>>>> phase accumulator. it does FM, sync, and triangle output. the normal
>>>> waveforms are provided with analog waveshapers. i'm especially happy
>>>> with the sine shaper which uses the OTA with feedback method. it
>>>> tracks 1v/oct very closely. i also added a linear fine frequency
>>>> offset added after the expo conversion to set constant beating but
>>>> i've only built one of these so far. aliasing is not an issue since i
>>>> sample at 500KHz and have a 2nd order (100khz fc) at the output.
>>>> really the only issue i have is that it is a power hog. it uses 120mA
>>>> off the +15v  supply. most of that is the dspic since it runs at
>>>> 120MHz.
>>>>
>>>> all the documents and a few sound tests are posted on my website.
>>>> http://www.homebuilthardware.com/index.php/projects/dspicvcdo/
>>>>
>>>> -Ryan
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