[sdiy] dspic VCDO

[Csaba Zvekan]

Hi Ryan,

Great work on your VCDO . I was wondering why you used a 30MHz crystal  
in your design with PLL ? I thought that 4-10MHz was the maximum clock  
allowed .  Do you really  need the 4x PLL to get the 120MHz?
I don't think I need to tell you that the slower you clock the less  
current it's being consumed.
But also have you considered the dsPIC33Fxxxx series with nanowatt  
technology ?

Csaba

On Aug 15, 2008, at 8:26 PM, ryan williams wrote:

> hi all,
>
> i built a new module a VCDO programmed in a dspic w/16bit ADC. exp
> conversion is done with a lookup table. 24bit tuning word and a 32bit
> phase accumulator. it does FM, sync, and triangle output. the normal
> waveforms are provided with analog waveshapers. i'm especially happy
> with the sine shaper which uses the OTA with feedback method. it
> tracks 1v/oct very closely. i also added a linear fine frequency
> offset added after the expo conversion to set constant beating but
> i've only built one of these so far. aliasing is not an issue since i
> sample at 500KHz and have a 2nd order (100khz fc) at the output.
> really the only issue i have is that it is a power hog. it uses 120mA
> off the +15v  supply. most of that is the dspic since it runs at
> 120MHz.
>
> all the documents and a few sound tests are posted on my website.
> http://www.homebuilthardware.com/index.php/projects/dspicvcdo/
>
> -Ryan
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