[sdiy] DC offset removal help

[Tim Stinchcombe]

> It's the old EFM Dual ADSR...running off of a 556.  I don't 
> know if there are schematics online.  But like I said, there 
> is essentially a .2 V offset right after gate, and it 
> eventually settles to .1 V.

If the schematic I have for that is the one you have, then I think that the
residual 100mV is the collector-emitter saturation voltage of Q2, which is
hard on with no gate applied (the main cap discharges through the release
pot, a diode and then Q2). Thus if you could find a nifty way of lowering Q2
emitter, wthout upsetting the gating action, then that would probably solve
it - I actually have a simulation of that circuit from years ago for another
problem, but at the moment I'm fresh out of 'simple' ideas that might work
(brain addled from a long day...)

Tim
__________________________________________________________
Tim Stinchcombe 

Cheltenham, Glos, UK
email: tim102 at tstinchcombe.freeserve.co.uk
www.timstinchcombe.co.uk