[sdiy] Function Generator ICs

[David Betz]

>>> BTW, I don't totally
>>> understand the "gate count" thing, I have the "500K gate" Spartan-3E
>>> (XC3S500E), oddly though, in my polysynth design, the ISE says the
>>> design represents 1,290,000 "equivalent" gates...
>>
>> The gate counts don't really tell you anything useful unless you are
>> comparing them across the same set of tools.  In theory they should
>> give you an idea how costly it would be to implement your design  
>> as an
>> ASIC.  These numbers have been going through various iterations of
>> marketing fudge factors with each generation of the FPGA architecture
>> (not just at Xilinx).  A system gate is supposed to be equivalent to
>> the sea-of-gates available in some mask programmed gate arrays.
>
> It used to be a almost meaningfull measuring method. But with the  
> LUTs, CLBs
> and other larger blocks, the lines have become fuzzier. I just  
> don't use it
> anymore for FPGA work. It is a meaningless measure now. Ths fit- 
> size into a
> certain architecture gives better feeling. 495 CLBs in Virtex 2VPX  
> says more
> (if you used and encountered one... :).

The only use I make of "gate counts" is to compare two FPGA chips in  
the same family. I'm assuming that a Xilinx Spartan 3 that claims  
"1000k gates" will hold five times as much logic as one that claims  
"200k gates". Is that a safe assumption?