[sdiy] Buffered CV inputs with SSM2164 Quad VCA?

[Derek Holzer]

I'm working off the spec sheet for the SSM2164 Quad VCA, and I want to 
set it up to receive CV from other modules in my Doepfer. The spec sheet 
describes a situation where a pot is used to generate CV:

> For this example, the control voltage is developed using a
> 100kΩ potentiometer connected between +5V and ground.
> This configuration results in attenuation only. To produce both
> gain and attenuation, the potentiometer should be connected
> between a positive and negative voltage. The control input has
> an impedance of 5kΩ. Because of this, any resistance in series
> with VC will attenuate the control signal. If precise control of
> the gain and attenuation is required, a buffered control voltage
> should be used.

http://www.analog.com/en/prod/0,2877,SSM2164,00.html

So, with this in mind, can I wire an input jack straight into the VC 
input of the SSM2164, perhaps through a resistor and decoupling cap, or 
does it need an op amp buffer? And if it needs such a CV buffer, can 
someone point me to a simple schemo or explanation of what it takes to 
make one? (Actually, I'd like to learn more about it anyways...)

Thanks for any tips!
derek

-- 
derek holzer ::: http://www.umatic.nl ::: http://blog.myspace.com/macumbista
---Oblique Strategy # 195:
"Describe the landscape in which this belongs."