FW: [sdiy] Tempo/Clock-to-CV conversion

[Needham, Alan]

Florian Anwander wrote:
...[snip]...
> My first idea looks like that:
> A binary counter is counting down at a fixed rate. The output of the 
> counter is D/A converted (resistornetwork), and the resulting voltage 
> feeds a S&H stage.
> The positive edge of the incoming clocksignal clocks the sample&hold
> and (a little bit delayed) resets the counter.

How about just latching the binary down-counter's value at 'RESET'
and using the latch to drive a DAC, every clock period is measured,
no S&H drift to worry about
A nice little microcontroller project (a single-chip solution) ?


> Pulse length will be converted too (to quite short pulses).

Is this a second conversion, one of period, one of pulse width ?

	Alan

_____________________________________________________________________
The information contained in or attached to this email is intended only for the use of the individual or entity to which it is addressed. If you are not the intended recipient, or a person responsible for delivering it to the intended recipient, you are not authorised to and must not disclose, copy, distribute, or retain this message or any part of it. It may contain information which is confidential and/or covered by legal professional or other privilege (or other rules or laws with similar effect in jurisdictions outside England and Wales).
The views expressed in this email are not necessarily the views of Centrica plc, and the company, its directors, officers or employees make no representation or accept any liability for its accuracy or completeness unless expressly stated to the contrary.

Centrica plc

Registered office: Millstream, Maidenhead Road, Windsor, Berkshire SL4 5GD

Registered in England and Wales No 3033654