[sdiy] ceramic capacitor voltage rating

[John Luciani]

On Nov 24, 2007 6:49 PM, Daniel Kruszyna <dan at krue.net> wrote:
> I've heard the rule of thumb to use twice the expected
> voltage rating for decoupling capacitors, but am
> wondering how necessary it is. Particularly, I'm working
> on a fairly dense surface mount pcb and the voltage
> rating determines the minimum package size I can use.

For an aluminum electrolytic or a tantalum capacitor that
is good rule of thumb (for *typical* decoupling applications).
For a ceramic capacitor it can be overkill (depending on the dielectric).

> I thought that this spec looks pertinent:
>
> ------------------------------------------
>   Dielectric
>   Withstanding
>   Voltage
>
>   No dielectric breakdown and/or damage
>
>   Test voltage : Rated voltage 250 %
>   Duration:1 to 5 s.
>   Charge / Discharge current: 50 mA max.
> ------------------------------------------
>
> Should it be okay to use less of a margin than x2?

That is one specification that is pertinent. Another would be
percent capacitance change versus DC bias voltage. If you
are using X7R dielectrics you are probably OK but you should check
the graphs. There was an application note from Kemet or AVX
that discusses the voltage rating. I thought I had a copy but I
can't seem to find it right now :-(

In a *typical* decoupling application I would use an X7R ceramic
capacitor up to its voltage rating.

(* jcl *)

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