[sdiy-interim] JH VCS3 SAmple and Hold

[JH.]

There's always the possibility of errors in my circuit drawings, but I've 
looked at it again and it really looks as it should be.
(Certainly no intentional / anti-dopeferizing errors here.)
I recommend testing the circuit backwards from the S&H stage (upper right 
corner).
Does the OTA get the right sample pulses in its iabc pin, will it sample 
when you apply external pulses (30k resistor connected to positive supply, 
other end manually touching the iabc pin ...), and so on.

JH.


----- Original Message ----- 
From: "ganesha" <goaqihai at yahoo.co.uk>
To: "RichR" <rrowley at btinternet.com>; <synth-diy at vermine.org>
Sent: Saturday, March 31, 2007 10:53 AM
Subject: Re: [sdiy-interim] JH VCS3 SAmple and Hold


Hi,
I didn't make it yet, but I'm going to. I already made
a pcb and drilled all the holes, but I still need to
solder the components. I don't know when it will be
finished, because it is part of a larger project and
I've started with an other pcb first. I'll let you
know when I'm done. In the mean time, if you find the
problem I would like to hear what it was.
regards,
Kris
--- RichR <rrowley at btinternet.com> wrote:

> Hi All
> I wondered if any of the list had made this circuit
> with success?
>
> http://jhaible.heim.at/tonline_stuff/jh_sc_shg.html
>
> I've made it twice slavishly following the schematic
> but all i end up with
> is a fixed +10v on the output
>  I'd be really gratefull of any help
>
> Cheers
> Rich
>
>
>
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