[sdiy-interim] EPROM Armageddon?

[ASSI]

On Mittwoch, 28. März 2007 14:26, Mike wrote:
> Thre is evidence, (and I can't find the article at the moment), thta
> retention time is unfluenced by usage.

Apart from temperature, that is no concern for EPROM.  EEPROM or FLASH 
is a different matter, some concepts have so-called read disturbs, 
which means that reading a cell more often will degrade the stored 
charge.

> The article suggested longer times if in use.

I can't think of any reason why that would be the case.

> There was also a suggestion that the more recent 
> high density ones are subject to data erosion due to smaller gate
> area, (less charge per bit),

They certainly have less charge per bit, but then they also lose less 
charge through the smaller gate area.  It's a zero-sum game as long as 
the scaling works perfectly.  The charge retention that is routinely 
achieved is amazing: for a modern technology you are allowed to lose a 
single electron about every three weeks.  Your old EPROM loses a lot 
more in that time frame, but then it has a lot more to start with.

> and cosmic ray bombardment 

No.  DRAM (of the 1-16MBit vintage) and SRAM (about 150nm and below) is 
susceptible to this, but not EPROM/EEPROM/FLASH.  There are enough 
rad-hard qualified technologies out there to prove that.

> And what about the ongoing 'Chipmageddon' anyway.....gate migration
> is taking out a lot of older CMOS

There is stress migration and electromigration, but none of that usually 
happens on the gate (not even if it's a metal gate).  Really old CMOS 
parts may be dying from BTS (bias-temperature stress) drift due to 
mobile ions and no or insufficient diffusion barriers.  Highly scaled 
CMOS can drift due to HCS (hot carrier stress), but this does not 
usually kill a chip.  The simplest chip-kill would still be corrosion 
and lifting of the bond pad.



Achim.
-- 
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