[sdiy] Verilog Uart

[James Patchell]

For those of you who might be interested....I just posted an updated UART 
written in verilog for the Xilinx Spartan 3....

http://www.noniandjim.com/Jim/IpArchive/HdlArchive.html#Uart_Softcore

This is a bit more complete...it has only been simulated, not actually 
tested in hardware...

It features:

16 deep send and receive fifos
Interrupts
Baud Rate Generator

I am going to update it again in a few days so that the top file will have 
documentation on how it works.

Uses no xilinx cores.  It does use a Xilinx Dual Port Ram Primative...but 
it should be easy to port over to other FPGA's, I would think.  It has an 8 
bit bus.


         -Jim
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http://www.oldcrows.net/~patchell
http://www.noniandjim.com/
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