[sdiy] ARM vs dsPIC performance

[Robin Whittle]

I wonder how the ARM microcontrollers compare with the latest dsPIC
microcontrollers for execution speed.

For instance, the ARM Stamp:

   http://www.futurlec.com/ET-ARM_Stamp.shtml

uses a Philips (NXP) LPC2119 with 128kB FLASH and 16kB RAM:

   http://www.nxp.com/acrobat_download/datasheets/LPC2119_2129_4.pdf

The CPU type is "ARM7TDMI-S":

   http://www.arm.com/pdfs/DDI0234A_7TDMIS_R4.pdf

I tried to figure out the instruction cycles required for a multiply
accumulate operation, but didn't spend the time to figure it out fully.
 My initial impression, from pages 7-5 and 7-12 of that PDF is that a 16
bit multiply-accumulate instruction takes 6 cycles (table 7-8).  A long
(32 bit I guess) multiply accumulate (table 7-10) takes 7 cycles.

I don't know how fancy the addressing modes are, with auto increments
etc.  In the ET-ARM Stamp, the chip runs at 58.9824MHz, so I guess a
multiply-accumulate takes about 100ns.

Compare this with a dsPIC, running at 40 MIPS:

  http://www.microchip.com  > 16-bit PIC® MCUs & dsPIC® DSCs
  > dsPIC33 DSC > dsPIC33FJ128GP706

This also has 128kB FLASH and 16kB RAM.  It has two CAN interfaces, but
other versions not yet on sale have no CAN, and will presumably be
cheaper than the USD$5.49 quoted.  This is a 64 pin device, and it has a
proper "codec" interface to digital audio DACs.

I have programmed a 30 series dsPIC and found it to be a good device,
with nifty nooks and crannies which need to be researched, and with a
good, free, integrated development system.  I only programmed in
assembler - the C compiler costs money and I didn't want it anyway.

The dsPIC 33 Family Datasheet is:

  http://ww1.microchip.com/downloads/en/DeviceDoc/70165d.pdf

These are 16 CPUs with 17 bit multiply and 40 bit accumulation.  There
is a fancy multiplication system, which I can't remember the exact
details of now, involving RAM being in two sections which can be
simultaneously read, which enables the fetching of the two operands
(based on registers set up for various auto increments) and the
accumulation of the result in a single CPU cycle.  Actually, I recall it
grabs operands which are already in place and while it is doing the MAC
operation, it gets the operands ready for the next time the MAC
operation is run.  The MAC instruction is listed on page 302 as being
one cycle.  Section 2.6 describes the "DSP Engine".

Without doing a lot of research, it is my impression that a 40 MIPs
dsPIC, programmed in assembler, would be faster than this 60 MHz ARM
chip, for general 16 bit DSP operations.

 - Robin          http://www.firstpr.com.au/rwi/dfish/