[sdiy] Clock generation

[Eric Brombaugh]

Tom Arnold wrote:
>> * What switched cap filter are you using? 
>>     
> For various reasons I'm using ones from Mixed Signal.  They offer 50:1 and
> 100:1 ratios. 7pole.  Good price.  Good people to deal with.
>
>   
Ok - I grabbed a few datasheets off their site. Looks like some of the 
more highly integrated switched-cap filters out there - not a lot of 
user configurability. I'm more used to the classic 'building-block' type 
like the old Nominal Semidestructor MF10 and the Linear Tech LTC1060. 
They require a few more resistors but give a lot of options on topology 
and ratios.

One thing you shouldn't forget is Nyquist! BBDs (and switched cap 
filters for that matter) are sampled devices. The filter has a fixed 
ratio between the corner frequency and the clock frequency. The corner 
frequency should be set to 1/2 (or less) of the BBD clock rate. This 
means that if you choose a filter with a 50:1 Fclk/Fc ratio, you should 
only run it 25x the BBD frequency to avoid passing frequencies greater 
than the BBD Nyquist rate.

>> * You could use 1 VCO to generate the BBD clock over the full 
>> 10kHz-100kHz range and a 4046 PLL to generate 50x clock for the 
>> switched-cap filter from that rate.
>>     
>
> I didnt consider using a PLL because of the tracking slop, but I suppose I
> should since we're talking about fairly slow rates of change it wouldnt be
> bad at all.
>   
A PLL would ensure a precise tracking between the filter Fc and the BBD 
clock rate (up to the filter max clock rate), but that's probably not 
ultra-critical. Two 555 timers set to run roughly 25x different would 
probably work fine.

> One thing I have pondered would be using a microcontroller to generate the
> clock.  The code would be trivial, the two clocks would track each other
> dead-on.  The parts count would be low.  Use an A/D to track the inbound CV
> and set the timing loop.   Might not be a bad way to do it
That's attractive from a 'gee-whiz' standpoint, but I'd be really 
careful about driving your audio sampling clocks from a microprocessor. 
The processor can't generate accurate jitter-free clocks since it can 
only create edges at integer multiples of its own clock period. That 
means your BBD and switched cap clocks will be jittering like crazy, 
introducing all kinds of phase distortion into the audio signal. That 
might be interesting/useful in some situations, but less than ideal for 
most applications.

Eric