[sdiy] Clock generation

[Eric Brombaugh]

Hmmm...

A couple of questions:

* What are you using for a VCO? I've always used the CD4046 for that and 
it seems to top out around 1-2MHz. The 74HC4046 is good to 10MHz though 
and is a pin-for-pin replacement for Vdd<6V.

* What switched cap filter are you using? By choosing the right resistor 
ratios you can alter the Fclk/Fc ratio on some of them. That way you 
don't need to operate the filter at 50x the BBD clock.
 
* You could use 1 VCO to generate the BBD clock over the full 
10kHz-100kHz range and a 4046 PLL to generate 50x clock for the 
switched-cap filter from that rate. Use the 4046 VCO range limit 
resistors to make sure it tops out at ~1MHz to keep the filter happy. 
The PLL will lose lock when the BBD clock exceeds 20kHz, but you may not 
care about the filter tracking beyond 20kHz anyway. It will still 
anti-alias at those high rates.

Eric

Tom Arnold wrote:
> So, I'm back to playing with BBDs again, I'm also playing with some switched
> cap filters I got from MSI.  I need to generator an interesting pair of
> clocks.
>
> The BBD needs a clock from 10khz or so up to 100khz or so.   The filters
> need 50 times that with a max of 1mhz.
>
> My first thought was to divide down the filter clock to get the BBD clock
> which wont work because that would give me a max BBD clock of 20khz.  I could
> multiply the BBD clock to get the Filter clock, but I'd exceed the max clock
> of the filter.  So what I've been pondering is a pair of linear VCOs because
> I could fairly easily scale+limit the input to the filter clock so I wouldnt
> exceed the max freq of the filter, and the BBD vco would be able to run to
> 100khz plus I'd get the bonus of voltage control of the clock.
>
> I'm betting I've missed a far simpler way of doing this which I'm hoping
> someone will point out...
>
>