[sdiy] ripple counters

[mark verbos]

That circuit is one of my referances, however the circuit that derives 
the various signals from the clock is poor. Because it relies on those 
150p caps, it's range is limited. Deltalab did a configuration that uses 
AND gates with resistors between them to get short delays and create the 
signals for the RAM.  Check out the Echotron or Effectron if you can. 
They operate the circuit at +12 volts, but I couldn't tell you if that 
matters to the timing. They use 40193 synchronous counters in all the 
versions I've seen.

Incidentally, Buchla used this same technique in his delay modules, but 
he used serial I/O shift registers insted of RAM. Electronics and 
Wireless World's encoding/decoding is the simplest I've seen though.

Harry, I think you answered my question. I'll change it to 40193s after 
all, I don't want the headaches later. After all, it's just a couple chips.

Mark




Eric Brombaugh wrote:

> The circuit he's talking about may be this one:
> 
> http://www.all-electric.com/b&c.html
> 
> Basically, it has a home-made 1st-order Sigma/Delta ADC generating a 
> 1-bit datastream that's stored in a 4164 DRAM configured as a 64k 
> circular buffer. They use a pair of 'LS393s and a pair of 'LS157s to mux 
> a 16-bit address down onto the 8 multiplexed address bits of the DRAM. 
> The DRAM latches the address based on the RAS/CAS signals, so you need 
> to ensure the counters are stable when those signals pop. I haven't 
> looked closely at the control logic so I can't tell you if this 
> constraint is met, but there are what appear to be caps hanging off of 
> gate outputs, so it may be a tad hairy.
> 
> It's a pretty nifty idea and a great way to get a delay line without 
> using BBDs. :)
> 
> I've been thinking about building something derived from this for a 
> while. Those ancient 41XXX DRAMs are really cheap (less than a buck from 
> Jameco) and it would be a hoot to see how well this works.
> 
> Eric
> 
>