[sdiy] SEAForth-24 (was: Re: FPGA Starter)

[Daniel Kruszyna]

asfi at eol.ca <asfi at eol.ca> wrote:
> Interesting, and strangely reminiscent of Inmos, right down to the
> relatively slow inter-chip links. They're bucking the trend on that
> one, though gigabit-LVDS interfaces would require gobs of buffer RAM
> to prevent the handshake-and-vegetate from slowing everything to a crawl. 

The pdfs don't specify the external link speed, but the internal links run
at the speed of the silicon. The INMOS chips had only one core apiece, making
all links inter-chip. Also, the c18 cores each have their own RAM for program
storage, so the main task is getting data to "flow" efficiently across
the grid.

Or do you mean slow in that each core can only talk to the four adjacent
cores? (and any other destination needs to be forwarded)

> The use of Forth is perhaps the most interesting feature. In my experience,
> high-quality (multi-)media development projects for honkin' embedded chips
> are multi-manyear efforts. It would be neat to shave that down to a more
> human scale. 

Yes, I hope it catches on.

-- Daniel (who gets strange looks at interviews from listing Forth on his resume)