[sdiy] Place to start with 3E dev kit

[Rainer Buchty]

> To emulate that on a typical FPGA you're going to need to come 
> up with accurate DSP models for the multi-mode filter, which while not 
> impossible may be quite time consuming. Without the filter it's really 
> not a SID.

Have a look into the reSID sources, e.g. to be found in VICE:
	http://www.viceteam.org/

You'll even find some schematics about the (possible) innards of the SID 
filter. Plus, of course, plenty of C++ code.

The Syntiac VHDL sources are developed further to become a full-blown 
C64 core for the C-One reconfigurable computer:
	http://c64upgra.de/c-one/

or, more specifically,
	http://c64upgra.de/c-one/download/fpga64_alpha4_src.zip

Alas, that one is Altera-based, so tuning it to Xilinx might involve 
some work.

Rainer