SV: Re: [sdiy] Xilinx 3E webpack and its gotcha's!

[Magnus Danielson]

From: Eric Brombaugh <ebrombaugh at earthlink.net>
Subject: Re: SV: Re: [sdiy] Xilinx 3E webpack and its gotcha's!
Date: Wed, 14 Jun 2006 08:13:45 -0700
Message-ID: <449027A9.1000303 at earthlink.net>

> Magnus Danielson wrote:
> > I have somehow been given the impression that Verilog is strong in the USA and
> > VHDL is strong in Europe. Assuming that this is fairly "right", one may
> > experience one of them as being more common.
> >   
> 
> I've heard this too and it strikes me as odd considering that VHDL was 
> developed under a US Gov't DARPA contract *. So much for parochialism.

While Verilog comes out of a particular vendor.

Originally VHDL was poorly suited for synthesis, since it really was intended
for simulation, and this is also a reason for the strictness of the languague,
but the synthesis aspect grew more and more.

> BTW - sorry for bringing up this old canard. The "your programming 
> language vs my programming language" argument is probably older than 
> computers and does very little to advance understanding. Personally, 
> although I don't use VHDL, I believe that competition between similar 
> solutions strengthens both. As Jim said, these days the end result is 
> the same so it boils down to what the individual prefers.

Indeed.

Didn't the Verilog and the VHDL organisations merge eventually? Ah well.

Cheers,
Magnus