SV: Re: [sdiy] Xilinx 3E webpack and its gotcha's!

[Magnus Danielson]

From: Eric Brombaugh <ebrombaugh at earthlink.net>
Subject: Re: SV: Re: [sdiy] Xilinx 3E webpack and its gotcha's!
Date: Wed, 14 Jun 2006 06:06:23 -0700
Message-ID: <449009CF.2060803 at earthlink.net>

> Paul Maddox wrote:
> > that would be superb, if a couple of the 'pro' VHDL people could write 
> > a couple of 'hello world' examples.
> 
> I guess that rules me out since I use Verilog. :)
> 
> Seriously though, what's the consensus on HDLs? I know that for a long 
> time VHDL was more popular than Verilog in the FPGA world, but from what 
> I can tell the tools are agnostic on that point today. Verilog was more 
> popular in the ASIC design world, but due to the increased popularity of 
> FPGAs, a lot of us old-time ASIC designers are now finding ourselves on 
> the other side of the fence.

The "design world" is infact quite divided still. There is no winner and I
think the discussion as such is dated. I use VHDL and so does several others.

> I've never seriously tried to do VHDL, but looking at the code always 
> makes my head hurt. When I compare code snippets in the FPGA 
> documentation that demonstrate how to do something in both languages, 
> the VHDL examples are always 2-3x longer than the Verilog ones.

While I have looked at many Verilog sources just to find them unreadable.
Face it, the other language looks like the ugly child depending from your
own preference, but that doesn't boil down to a real truth. We do large designs
in VHDL and it works well. The whole issue about "2-3x longer" is IMHO pure
bogus and doesn't really measure anything about usefullness.

> Based on that, I guess I'm surprised that more beginners aren't drawn to 
> Verilog over VHDL.

After what I've seen I am suppriced so many still persists on using Verilog.
Neither of these personal views means anything in the end. They are just
different views based on different experiences, gain from different backgrounds
etc. VHDL works splendid for both small and large projects. As for how Verilog
works, I assume people would feel the same way.

Last time I looked into the Verilog LRM (I have a hardcopy from IEEE) I
concluded that it was a not too well defined languague and infact I had to use
some of my more obscurer knowledge in C and interpolate with what the LRM said
in order to conclude on the correctness in a certain Verilog model which
someone claimed to be invalid Verilog and was quite supprised to find that the
golden reference actually accepted. In contrast is the VHDL LRM actually quite
complete, but it is on the other hand hard to correctly interprent unless you
spent some time with it.

So, there is no and will never be any real winner in the Verilog vs. VHDL
battle. These are the two languagues that has to be supported and one cannot
make the assumption that one is better than the other.

Cheers,
Magnus