[sdiy] Xilinx 3E board comments

[Magnus Danielson]

From: James Patchell <patchell at cox.net>
Subject: Re: [sdiy] Xilinx 3E board comments
Date: Tue, 13 Jun 2006 15:21:07 -0700
Message-ID: <5.2.1.1.2.20060613152018.0181cf38 at pop.west.cox.net>

> Good advice...but, if you know how to avoid "hazards" and "races"...it is 
> possible...but boy, the tools sure complain about it :-)

Some asynchronous designs you can't even realize without going VERY WIDE
CIRCLES around the normal path. The tools will not complain tons about it, they
will just plainly refuse to comply!!!

For example, when I was attempting to do a normal blocked RS-flip-flop, however
I attempted to express it, the tools did not like the feedback-loop in the
logical statements. In normal design you would _never_ do this. However, when
looking into what Xilinx provides as instantiable logic, I found a gate which
when hooked up properly does what I want, asynchronously and all.

A straight-forward implementation from my schematic would have me hook up four
NAND-gates. That failed misserably!

Cheers,
Magnus