[sdiy] Xilinx 3E board comments

[Magnus Danielson]

From: jhaible at debitel.net
Subject: Re: [sdiy] Xilinx 3E board comments
Date: 13 Jun 2006 10:51:06 +0200,Tue, 13 Jun 2006 10:51:06 +0200
Message-ID: <1150188666.448e7c7a29f31 at www.debitel.net>

> > I'm not familiar with that very Oberheim, but all you will be able to do 
> > is synthesize the *digital part* of the schematics. 
> 
> It is just digital, plus DAC and S&H.
> 
> > And even those 
> > possibly not 1:1 if they play nasty tricks like prolonguing and 
> > delaying signals using 7406 and attached R/C where the timing was in a 
> > way that it matched the specific ratings of the used technology (74, 
> > 74LS, 74F, ...)
> 
> Oh yes, you're right. Could be replaced with (a lot of) gates and their
> propagation delay, or a counter or whatever, but it won't be as straight
> forward as it might look at the first glance.

If you just put a line of inverters in the VHDL code then the would be
(correctly) reduced to a single inverter or no inverter whatsoever. To get them
you need to instantiate them explicitly. However, longer delays (many gate-
delays) is best nacheived by sampling through DFFs. Then again, this only shows
that you approach the problem on a too low level, you try to imitate the low-
level details of that implementation. Back up and see what the overall plan is
and then re-implement that into a synchronous clock design. Rising edge
detection is for instance two DFFs and a LUT (XOR function).

At first the tools may be a bit strange, but you learn pretty quickly.

Cheers,
Magnus