[sdiy] Xilinx 3E board comments

[Rainer Buchty]

>I have next to zero VHDL skills (except for a 2 day "mangement" VHDL
>crash course), but if I got this right, I could just use the Oberheim
>_schematics_ and then synthesize (pun) them.

I'm not familiar with that very Oberheim, but all you will be able to do 
is synthesize the *digital part* of the schematics. And even those 
possibly not 1:1 if they play nasty tricks like prolonguing and 
delaying signals using 7406 and attached R/C where the timing was in a 
way that it matched the specific ratings of the used technology (74, 
74LS, 74F, ...)

Rainer