[sdiy] Single chip digital delay

[René Schmitz]

Hi Seb and all,

you also might want to have a look at the delay line at my website.
I've been using 64 and 256kBit DRAMs as the FIFO.

Then there is also a schematic that is on Batz' Site which used a D-Type 
FF and an RC-integrator in pretty much the same way as proposed in the 
second link. http://all-electric.com/schematic/ddl.htm
The only difference is that the output is latched by the FF, so there 
are no problems with sampling on a transitioning signal.

Seb Francis wrote:

> Thanks for these links.  The 2nd one looks interesting - I hadn't 
> thought of making my own 1-bit oversampled ADC/DAC and just stringing 
> some FIFO memory in between.  I think your calculations for the memory 
> storage are not quite right though: should simply be the sampling rate * 
> the time to give the number of bits needed.  But for this kind of 
> conversion it probably needs a sampling rate of somewhere near 1MHz is 
> needed to get decent quality .. so 10ms delay = ~10kbit (pretty much the 
> same result as calculating it based on 'normal' sampling rate and 16bit 
> resolution).

Mind that with such a simple converter you need to supersample the 
signal, so a much higher rate than 16*44.1k would be desireable. Else 
you will have problems with fast transients in your signal. (SAW, 
PULSE...) The Adaptive Delta Modulators (from a deltalabs patent) which 
I used reduce this requirement. And there I ended up at rates of about 
500kHz-1MHz for good reproduction.


Cheers,
  René

-- 
uzs159 at uni-bonn.de
http://www.uni-bonn.de/~uzs159