[sdiy] PCB layout rules

[John Luciani]

On 12/22/06, Paul Perry <pfperry at melbpc.org.au> wrote:
> Here's a problem though.... what do we mean by "sdiy frequencies"?
> Edges of clocks, spikes as oscillators turn over, microprocessors....
> there's a lot happening in most sdiy that involves high speed transitions.

How high are the switching currents? What is the impedance of your ground?
This is another reason to use the logic family that has slowest edge speed that
will meet the system specifications.

> To say nothing of crap like LEDs that have to be kept separate.
> You can't sweep it under the carpet unless you have a REALLY DEEP
> carpet!

I am assuming you mean PWM driven leds since at DC the ground plane
is 0 ohms. If you have very high currents you could need to split planes.
A few mOhms per square at 100MHz is a fairly low resistance. Splitting
the planes will depend on the accuracy you require.

> Though if you mean, the analog ground, the digital ground, and the plane are
> three separate nets that connect at one common point only, then yes, I
> agree.

If you start chopping the planes you may increase the number of squares
and the impedance of each plane. If you tie them together at single point you
won't have loops just higher imepedance planes.

Whether to separate the planes depends on the switching currents and amount
of noise you can tolerate. If you large high frequency switching
currents and require uV accuracy you will need to split the planes.

(* jcl *)


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