[sdiy] PCB layout rules

[John Luciani]

On 12/22/06, Antti Huovilainen <ajhuovil at cc.hut.fi> wrote:
> On Fri, 22 Dec 2006, Harry Bissell Jr wrote:
>
> > One per IC power pin per voltage... so the tpyical
> > opamp gets two.
>
> Doesn't this mean that the ground might get contaminated by power supply
> noise? From what I've understood, a cap is only needed between the rails
> for stability.

The cap is there for stability. It delivers surge currents through a
low impedance
path to the IC. Without the capacitor you would have the series inductance of
a much longer trace which would result in voltage dips and ringing at the Vcc
pin of your IC.

> Has anyone experimented with sense/force ground?
> Idea being that sense ground has minimal current through it and is only
> used for references and no loads.

The currents are probably not large enough in most sdiy applications to
require force and sense grounds. If you start chopping up your ground plane
you may create ground loops that will cause you more problems than the uV of
accuracy you gain.

I have used force and sense grounds in a 200A current sink and various
DC-DC converter test systems. With the large currents and voltage drops
across connectors force and sense connections (kelvin connections) were
required.

(* jcl *)


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